1. Field of the Invention
The present invention relates to methods for fabricating a semiconductor device, and more particularly, a method for fabricating a semiconductor device, in which a semiconductor substrate is etched by photochemical wet etching, to form a rounded edge of a trench.
2. Discussion of the Related Art
In general, for isolation of the semiconductor device, the LOCOS (Local Oxidation of Silicon) process has been used. Thereafter, due to drawbacks of the LOCOS process, new isolation technologies have been developed actively, of which technologies such as PBL (Poly Buffer LOCOS), R-LOCOS (Recessed LOCOS), and so on, have been widely used. Because these technologies not only have complicated processes, but also can not completely prevent a Bird's Beak phenomenon (in which a silicon oxide film encroaches into a channel region), the LOCOS-based technologies have limitations in packing semiconductor devices to a high density. Moreover, the high step that may exist between surfaces of the active region and the field region of the silicon substrate requires a subsequent planarizing step for reducing the step height of the surfaces.
Recently, an STI (Shallow Trench Isolation) process has been introduced, in which above drawbacks are improved. Because the STI process has a better device isolation characteristic and a smaller occupying area compared to the LOCOS processes, the STI process is very favorable for packing semiconductor devices to a high density.
In STI, a trench is formed in an isolation region of a silicon substrate, an oxide film is filled in the trench by gap filling, and the oxide film is polished by Chemical Mechanical Polishing (CMP), to planarize both the oxide film in the trench and the silicon substrate. According to this, the oxide film is formed in the trench in the isolation region of the silicon substrate.
As the oxide film for gap filling the trench, O3-TEOS (Tetra-Ethyl-Ortho-Silicate) deposited by Atmospheric Pressure Chemical Vapor Deposition (APCVD) or by Subatmospheric Pressure Chemical Vapor Deposition (SACVD), or an oxide film formed by High Density Plasma Chemical Vapor Deposition (HDPCVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD), all of which have good gap filling and planarizing characteristics, are mostly used.
In the meantime, referring to FIG. 1A, in the related art STI, for an example, a buffer oxide film 11 and a nitride film 13 are formed on an entire surface of a semiconductor substrate 10, such as a single crystal silicon substrate, in succession. Then, a photoresist film PR pattern is formed on the nitride film 13 for exposing the nitride film 13 on the field region of the semiconductor substrate 10. The nitride film 13 and the buffer oxide film 11 are subjected to dry etching using the photoresist film PR pattern as an etch mask layer, to form an opening 14 which exposes a surface of the field region of the semiconductor substrate 10.
Referring to FIG. 1B, the semiconductor substrate 10 at the opening 14 is subjected to dry etching by using the photoresist film PR pattern as an etch mask layer, to form a trench 15.
Referring to FIG. 1C, after removal of the photoresist film PR pattern in FIG. 1B, an etched surface of the trench 15 is subjected to thermal oxidation to form an oxide film 17 for reducing etch damage to the etched surface of the trench 15.
Referring to FIG. 1D, an insulating film having a good gap filling property is filled in the trench 15, and subjected to chemical mechanical polishing until the oxide film 19 is flush with the nitride film 13.
Referring to FIG. 1E, the nitride film 13 is etched by phosphoric acid solution, to expose the buffer oxide film 11. The buffer oxide film 11 is etched by hydrofluoric acid solution, to expose a surface of the active region of the semiconductor substrate 10. Thus, the STI process is finished.
In the meantime, because upper edges and lower corners of the trench 15 may be sharp, the oxide film 17 is sometimes used or formed on the etched surface of the trench 15 for moderating the sharp edges and the corners. However, since the upper edges and the lower corners of the trench 15 may still be sharp or otherwise fail to form a round shape, field concentrations may result in the regions of the substrate at or near the upper edges and the lower corners. As a result of the field concentration, a leakage current from the trench 15 may increase, thereby adversely electric characteristics and/or yield of the semiconductor device.